/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef __ASM_ARCH_MX28_REGS_H
#define __ASM_ARCH_MX28_REGS_H

#define IMX_SRAM_BASE		0x00000000
#define IMX_MEMORY_BASE		0x40000000

#define MXS_APBH_BASE		0x80004000
#define MXS_BCH_BASE		0x8000a000
#define MXS_GPMI_BASE		0x8000c000
#define IMX_SSP0_BASE		0x80010000
#define IMX_SSP1_BASE		0x80012000
#define IMX_SSP2_BASE		0x80014000
#define IMX_SSP3_BASE		0x80016000
#define IMX_IOMUXC_BASE		0x80018000
#define IMX_DIGCTL_BASE		0x8001c000
#define IMX_EMI_BASE		0x80020000
#define IMX_OCOTP_BASE		0x8002c000
#define IMX_FB_BASE		0x80030000
#define IMX_CCM_BASE		0x80040000
#define IMX_POWER_BASE		0x80044000
#define IMX_LRADC_BASE		0x80050000
#define IMX_WDT_BASE		0x80056000
#define IMX_I2C0_BASE		0x80058000
#define IMX_I2C1_BASE		0x8005a000
#define IMX_PWM_BASE		0x80064000
#define IMX_TIM1_BASE		0x80068000
#define IMX_UART0_BASE		0x8006a000
#define IMX_UART1_BASE		0x8006c000
#define IMX_UART2_BASE		0x8006e000
#define IMX_UART3_BASE		0x80070000
#define IMX_UART4_BASE		0x80072000
#define IMX_DBGUART_BASE	0x80074000
#define IMX_USBPHY0_BASE	0x8007c000
#define IMX_USBPHY1_BASE	0x8007e000
#define IMX_USB0_BASE		0x80080000
#define IMX_USB1_BASE		0x80090000
#define IMX_SDRAMC_BASE		0x800e0000
#define IMX_FEC0_BASE		0x800F0000
#define IMX_FEC1_BASE		0x800F4000

#endif /* __ASM_ARCH_MX28_REGS_H */
