/* SPDX-License-Identifier: GPL-2.0 OR X11 */
/*
 * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
 */

#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H

#define	CLK_OSC_SYS		0
#define	CLK_OSC_AUD		1
#define	CLK_PLL0_OUT		2
#define	CLK_PLL1_OUT		3
#define	CLK_PLL2_OUT		4
#define CLK_CPUNDBUS_ROOT	5
#define CLK_DLA_ROOT		6
#define CLK_DSP_ROOT		7
#define CLK_GMACUSB_ROOT	8
#define CLK_PERH0_ROOT		9
#define CLK_PERH1_ROOT		10
#define CLK_VIN_ROOT		11
#define CLK_VOUT_ROOT		12
#define CLK_AUDIO_ROOT		13
#define CLK_CDECHIFI4_ROOT	14
#define CLK_CDEC_ROOT		15
#define CLK_VOUTBUS_ROOT	16
#define CLK_CPUNBUS_ROOT_DIV	17
#define CLK_DSP_ROOT_DIV	18
#define CLK_PERH0_SRC		19
#define CLK_PERH1_SRC		20
#define CLK_PLL0_TESTOUT	21
#define CLK_PLL1_TESTOUT	22
#define CLK_PLL2_TESTOUT	23
#define CLK_PLL2_REF		24
#define CLK_CPU_CORE		25
#define CLK_CPU_AXI		26
#define CLK_AHB_BUS		27
#define CLK_APB1_BUS		28
#define CLK_APB2_BUS		29
#define CLK_DOM3AHB_BUS		30
#define CLK_DOM7AHB_BUS		31
#define CLK_U74_CORE0		32
#define CLK_U74_CORE1		33
#define CLK_U74_AXI		34
#define CLK_U74RTC_TOGGLE	35
#define CLK_SGDMA2P_AXI		36
#define CLK_DMA2PNOC_AXI	37
#define CLK_SGDMA2P_AHB		38
#define CLK_DLA_BUS		39
#define CLK_DLA_AXI		40
#define CLK_DLANOC_AXI		41
#define CLK_DLA_APB		42
#define CLK_VP6_CORE		43
#define CLK_VP6BUS_SRC		44
#define CLK_VP6_AXI		45
#define CLK_VCDECBUS_SRC	46
#define CLK_VDEC_BUS		47
#define CLK_VDEC_AXI		48
#define CLK_VDECBRG_MAIN	49
#define CLK_VDEC_BCLK		50
#define CLK_VDEC_CCLK		51
#define CLK_VDEC_APB		52
#define CLK_JPEG_AXI		53
#define CLK_JPEG_CCLK		54
#define CLK_JPEG_APB		55
#define CLK_GC300_2X		56
#define CLK_GC300_AHB		57
#define CLK_JPCGC300_AXIBUS	58
#define CLK_GC300_AXI		59
#define CLK_JPCGC300_MAIN	60
#define CLK_VENC_BUS		61
#define CLK_VENC_AXI		62
#define CLK_VENCBRG_MAIN	63
#define CLK_VENC_BCLK		64
#define CLK_VENC_CCLK		65
#define CLK_VENC_APB		66
#define CLK_DDRPLL_DIV2		67
#define CLK_DDRPLL_DIV4		68
#define CLK_DDRPLL_DIV8		69
#define CLK_DDROSC_DIV2		70
#define CLK_DDRC0		71
#define CLK_DDRC1		72
#define CLK_DDRPHY_APB		73
#define CLK_NOC_ROB		74
#define CLK_NOC_COG		75
#define CLK_NNE_AHB		76
#define CLK_NNEBUS_SRC1		77
#define CLK_NNE_BUS		78
#define CLK_NNE_AXI		79
#define CLK_NNENOC_AXI		80
#define CLK_DLASLV_AXI		81
#define CLK_DSPX2C_AXI		82
#define CLK_HIFI4_SRC		83
#define CLK_HIFI4_COREFREE	84
#define CLK_HIFI4_CORE		85
#define CLK_HIFI4_BUS		86
#define CLK_HIFI4_AXI		87
#define CLK_HIFI4NOC_AXI	88
#define CLK_SGDMA1P_BUS		89
#define CLK_SGDMA1P_AXI		90
#define CLK_DMA1P_AXI		91
#define CLK_X2C_AXI		92
#define CLK_USB_BUS		93
#define CLK_USB_AXI		94
#define CLK_USBNOC_AXI		95
#define CLK_USBPHY_ROOTDIV	96
#define CLK_USBPHY_125M		97
#define CLK_USBPHY_PLLDIV25M	98
#define CLK_USBPHY_25M		99
#define CLK_AUDIO_DIV		100
#define CLK_AUDIO_SRC		101
#define CLK_AUDIO_12288		102
#define CLK_VIN_SRC		103
#define CLK_ISP0_BUS		104
#define CLK_ISP0_AXI		105
#define CLK_ISP0NOC_AXI		106
#define CLK_ISPSLV_AXI		107
#define CLK_ISP1_BUS		108
#define CLK_ISP1_AXI		109
#define CLK_ISP1NOC_AXI		110
#define CLK_VIN_BUS		111
#define CLK_VIN_AXI		112
#define CLK_VINNOC_AXI		113
#define CLK_VOUT_SRC		114
#define CLK_DISPBUS_SRC		115
#define CLK_DISP_BUS		116
#define CLK_DISP_AXI		117
#define CLK_DISPNOC_AXI		118
#define CLK_SDIO0_AHB		119
#define CLK_SDIO0_CCLKINT	120
#define CLK_SDIO0_CCLKINT_INV	121
#define CLK_SDIO1_AHB		122
#define CLK_SDIO1_CCLKINT	123
#define CLK_SDIO1_CCLKINT_INV	124
#define CLK_GMAC_AHB		125
#define CLK_GMAC_ROOT_DIV	126
#define CLK_GMAC_PTP_REF	127
#define CLK_GMAC_GTX		128
#define CLK_GMAC_RMII_TX	129
#define CLK_GMAC_RMII_RX	130
#define CLK_GMAC_TX		131
#define CLK_GMAC_TX_INV		132
#define CLK_GMAC_RX_PRE		133
#define CLK_GMAC_RX_INV		134
#define CLK_GMAC_RMII		135
#define CLK_GMAC_TOPHYREF	136
#define CLK_SPI2AHB_AHB		137
#define CLK_SPI2AHB_CORE	138
#define CLK_EZMASTER_AHB	139
#define CLK_E24_AHB		140
#define CLK_E24RTC_TOGGLE	141
#define CLK_QSPI_AHB		142
#define CLK_QSPI_APB		143
#define CLK_QSPI_REF		144
#define CLK_SEC_AHB		145
#define CLK_AES			146
#define CLK_SHA			147
#define CLK_PKA			148
#define CLK_TRNG_APB		149
#define CLK_OTP_APB		150
#define CLK_UART0_APB		151
#define CLK_UART0_CORE		152
#define CLK_UART1_APB		153
#define CLK_UART1_CORE		154
#define CLK_SPI0_APB		155
#define CLK_SPI0_CORE		156
#define CLK_SPI1_APB		157
#define CLK_SPI1_CORE		158
#define CLK_I2C0_APB		159
#define CLK_I2C0_CORE		160
#define CLK_I2C1_APB		161
#define CLK_I2C1_CORE		162
#define CLK_GPIO_APB		163
#define CLK_UART2_APB		164
#define CLK_UART2_CORE		165
#define CLK_UART3_APB		166
#define CLK_UART3_CORE		167
#define CLK_SPI2_APB		168
#define CLK_SPI2_CORE		169
#define CLK_SPI3_APB		170
#define CLK_SPI3_CORE		171
#define CLK_I2C2_APB		172
#define CLK_I2C2_CORE		173
#define CLK_I2C3_APB		174
#define CLK_I2C3_CORE		175
#define CLK_WDTIMER_APB		176
#define CLK_WDT_CORE		177
#define CLK_TIMER0_CORE		178
#define CLK_TIMER1_CORE		179
#define CLK_TIMER2_CORE		180
#define CLK_TIMER3_CORE		181
#define CLK_TIMER4_CORE		182
#define CLK_TIMER5_CORE		183
#define CLK_TIMER6_CORE		184
#define CLK_VP6INTC_APB		185
#define CLK_PWM_APB		186
#define CLK_MSI_APB		187
#define CLK_TEMP_APB		188
#define CLK_TEMP_SENSE		189
#define CLK_SYSERR_APB		190

#define CLK_END			191

#endif
